1. Field of the Invention
The invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for an in-plane switching (IPS) mode LCD device resolving a contact problem in a gate pad region and a method of fabricating the array substrate.
2. Discussion of the Related Art
Recently, as the society has entered in earnest upon an information age, there is a requirement in properties of a thin profile, light weight and low power consumption for a flat panel display.
The flat panel display device is classified into an emission type and a non-emission type depending on whether the flat panel display device emits light or not. Since the emission type flat panel display device emits light, the emission type flat panel display device dose not require an additional light source. However, since the non-emission type flat panel display device does not emits light, the non-emission type flat panel display device requires an additional light source. For example, the emission type flat panel display device includes a plasma display device, a field emission display and an electro luminance display device, while the non-emission type flat panel display device includes an LCD device.
Among these devices, LCD devices are widely used for notebook computers, monitors, TV, and so on, because of their high contrast ratio and characteristics adequate to display moving images and color images.
The LCD device includes first and second substrates and a liquid crystal layer interposed therebetween. Electrodes are formed on each of the first and second substrates. The first and second substrates face each other, and the liquid crystal layer is positioned between the electrodes. The liquid crystal layer is driven by an electric field induced between the electrodes on the first and second substrates such that the alignment of the liquid crystal molecules changes. As a result, images can be displayed by controlling light transmissivity.
A liquid crystal panel for the LCD device is fabricated through a step of forming an array substrate, a step of forming a color filter substrate, a step of injecting a liquid crystal layer and a step of attaching the substrates. For example, a pixel electrode and a thin film transistor (TFT) as a switching element are formed in the array substrate. A common electrode and a color filter layer including red, green and blue colors are formed in the color filter substrate.
FIG. 1 is a schematic plan view of an array substrate for an IPS mode LCD device according to the related art. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG. 3 is a cross-sectional view taken along the line III-III of FIG. 1.
In FIG. 1, a plurality of gate lines 10 along a first direction are formed in a display region AA, where images are displayed, of the array substrate 1 for the IPS mode LCD device. A plurality of data lines 40 along a second direction are formed in the display region AA. The gate line 10 crosses the data line 40 such that a pixel region P is defined. A plurality of common lines 18 are formed to be parallel to the gate line 10. The common line 18 runs across the pixel region P. A thin film transistor (TFT) Tr as a switching element is formed in each pixel region P. The TFT Tr is connected to the gate and data lines 10 and 40. A pixel electrode 80 having a plurality of bars is disposed in the pixel region P. The pixel electrode 80 is connected to a drain electrode 55 of the TFT Tr. A common electrode 20 having a plurality of bars is disposed in the pixel region P and connected to the common line 18. The bars of the common electrode 20 are alternately arranged with the bars of the pixel electrode 80.
A plurality of gate pad electrodes 22 and a plurality of data pad electrodes 45 are formed in a non-display region NA at a periphery of the display region AA. The gate pad electrodes and the data pad electrodes 45 are connected to an external driving circuit (not shown). In addition, a gate link line 13 for connecting the gate line 10 to the gate pad electrode 22 and a data link line 42 for connecting the data line 40 to the data pad electrode 45 are formed. The common line 18 extends into the non-display region NA. An end of the data line 40 is electrically connected to an auxiliary common line 50 through a connection pattern 83. The auxiliary common line 50 is parallel to the data line 40.
Referring to FIGS. 2 and 3 respectively showing a cross-sectional view of connection portions of the common line 18 and the auxiliary common line 50, the common line 18 is formed a the substrate 1, and the auxiliary common line 50 is formed on a gate insulating layer 22 on the common line 18. A passivation layer 60 is formed on the auxiliary common line 50. A first contact hole 64 exposing the common line 18 is formed through the passivation layer 60 and the gate insulating layer 22, and a second contact hole 66 exposing the auxiliary common line 50 is formed through the passivation layer 60. The connection pattern 83 is connected to common line 18 through the first contact hole 64 and the auxiliary common line 50 through the second contact hole 66 such that the common line 18 is electrically connected to the auxiliary common line 50 through the connection pattern 83. The auxiliary common line 50 crosses the gate link line 13 which is connected to the gat pad electrode 22 (of FIG. 1). The gate link line 13 is formed at the same layer as the gate line 10 (of FIG. 1) and the common line 18. Accordingly, to prevent an electrical short between the auxiliary common line 50 and the gate link line 13, the auxiliary common line 50 is formed at a different layer than the common line 18.
However, when the auxiliary common line 50 is formed on the passivation layer 60 and in the first and second contact holes 64 and 66, there is a contact problem or an opening problem in the array substrate 1 for the IPS mode LCD device because of a step difference by the first and second contact holes 64 and 66 and an aligning deviation.
Moreover, since there are requirements for increasing an area of the display region AA and decreasing an area of the non-display region NA, decreasing a width of the auxiliary common line 50 is also required. In this case, there is a difference in a resistance at one end and the other end of the auxiliary common line 50. As a result, there is a difference in a common voltage applied to the common electrode 20 according to their position such that a displaying image quality is deteriorated.